(1) Field of the Invention
This invention relates to the planarization of an intermetal dielectric layer comprising spin on glass and more particularly to planarization using chemical mechanical polishing without etchback and having an automatic end point.
(2) Description of the Related Art
U.S. Pat. No. 5,094,972 to Pierce et al. describes the formation of a stop layer of CVD silicon nitride or CVD carbon on the surface of an integrated circuit wafer. Holes are formed in the stop layer and wells are formed in the material below the openings. After processing the device is planarized to the stop layer using abrasive mechanical polishing.
U.S. Pat. No. 4,956,313 to Cote et al. describes forming an insulator layer with holes. The holes are then filled with CVD tungsten which is also formed on the insulator layer. The metal layer and the insulator layer are then subjected to a polish etch in the presence of an abrasive slurry to remove the metal not filling the holes and to planarize the insulator layer.
U.S. Pat. No. 5,472,825 to Sayka describes planarizing a spin on glass layer without the use of a stop layer.
U.S. Pat. No. 4,997,789 to Keller et al. describes planarization using etchback with an aluminum etch stop layer.
U.S. Pat. No. 5,275,963 to Cedarbaum et al. describes planarizing a layer of phosphosilicate glass using chemical mechanical polishing without a stop layer.
This invention describes using chemical mechanical polishing to planarize an intermetal dielectric without using an etchback step. A hard metal cap formed on an electrode pattern is used as a stop for the chemical mechanical polishing step.